1. Field of the Invention
The present disclosure relates to semiconductor technology, and more particularly, to a package assembly having semiconductor chips stacked one on another and a method for manufacturing the same.
2. Description of the Related Art
With an increasing demand for miniaturization, light weight and multifunctionality of electronic devices, a semiconductor package is developed towards a high packaging density so that a package size can be reduced. A package assembly using a chip carrier and encapsulating a plurality of semiconductor chips has attracted attention. The chip carrier is, for example, a leadframe. A semiconductor chip is encapsulated in an encapsulant and electrically connected to external circuits by the leadframe. In other cases, the chip carrier is a printed circuit board. A semiconductor chip is mounted on the printed circuit board and electrically connected to external circuits by the printed circuit board. In such package assembly, configuration of the semiconductor chips and their connections have significant effects on the package size and properties of the electronic devices.
FIG. 1 is a perspective view showing a multi-level package assembly 100 according to the prior art. In the package assembly 100, the leadframe 110 includes a chip pad 111 and a plurality of finger-like leads 112. In a case that semiconductor chips are mounted on the leadframe 110 in two levels, as shown in FIG. 1, a lower-level semiconductor chip 120 has a bottom surface secured on the chip pad 111, and an upper-level semiconductor chip 130 has a bottom surface attached to a top surface of the beneath semiconductor chip 120 by means of an adhesive 123. Contact pads 121 are disposed at edges of the top surface of the semiconductor chip 120 and then electrically connected to the leads 112 by means of bonding wires 122. Contact pads 131 are disposed at a top surface of the semiconductor chip 130 and then electrically connected to the leads 112 by means of bonding wires 132. The leadframe 110 and the semiconductor chips 120 and 130 are encapsulated by an encapsulant layer 160. Outward portions of the leads 112 of the leadframe 110 are exposed from the encapsulant layer 160, for an electric connection with external circuits, such as a PCB (i.e. printed circuit board).
In the package assembly 100 according to the prior art, the semiconductor chip 130 needs to have a dimension (width, length, or both) smaller than that of the semiconductor chip 120 so that the edges of the beneath semiconductor chip 120 are exposed, which limits allowable size of the semiconductor chip.
Moreover, all of the input and output terminals of the semiconductor chips 120 and 130 need to be provided at the leads 112 of the leadframe 110 after being connected thereto by means of bonding wires 122 and 132. A number of the bonding wires may interference with each other, which results in poor high-frequency performance. Interconnect areas, with the number corresponding to the bonding wires, need to be provided at surfaces of the leads 112 of the leadframe 110. Consequently, the package assembly has a large size. Otherwise, less number of leads can be provided in the package assembly, which means less functionalities of the package assembly.
It is desirable that the multi-level package assembly has a small size with multifunctionality while improving electrical performance.